Test case (Summation of 1 to 9 ) given to RISC-V core implemented on FPGA

Using TL-Verilog for FPGAs

A few months back, I came across a workshop titled ‘RISC-V based Microprocessor for You in Thirty Hours (MYTH)’, that was about designing RISC-V core using TL-Verilog organized by Steve Hoover and Kunal Ghosh in just 5 days!! TL-Verilog must be magic to make this possible? Now I know the magic, and after completing the workshop, I was even more curious to know how we can use TL-Verilog for FPGA and thought of implementing my RISC-V core on FPGA.

Through this workshop, I came to know about how TL-Verilog is a Verilog implementation of TL-X, a language extension defined as a wrapper to any HDL to extend it with transaction-level modeling. This makes it more powerful and has a significant code reduction as compared to other HDL languages. To relate this to my own background, in my undergraduate, we had implemented MIPS Processor on FPGA in Verilog during a span of 3–4 months, and here I did it in just a span of 5 days!! I was so inspired by the workshop that I became a mentor. Other students along with me in the workshop, were interested in using TLV on FPGA, and there’s not yet much info about it, so I wanted to capture my experience here for others.

Before discussing how I implemented the core on FPGA, I would like to mention few points on the advantages of TL-Verilog over other HDL languages. TL-Verilog:

  • Introduces simpler syntax unlike other HDL like System Verilog or Verilog, hence reduces the number of lines in a code resulting in fewer bugs.
  • Is more flexible. Easier to optimize your logic without bugs.
  • Is “timing abstract” for pipelines, which makes retiming easy and safe.
  • Knows when signals are valid, which provides easier debug, cleaner design, better error checking, and automated clock gating.
  • Visual Debug (VIZ) is an additional feature to the Makerchip platform which makes the debugging process much easier. So, we dig into waveforms only when needed!
  • It supports “Transactions” and a simpler form of design hierarchy, which I haven’t had a chance to use yet, so I have even more to look forward to, myself.

The workshop was a great proof point for how easy it is to learn these powerful features vs. Verilog, as no one entering the workshop knew any TL-Verilog at the start. Many did not know Verilog either. In fact, I helped to mentor two students who were 12 and 13 years old who successfully completed the workshop!

Now I would walk through the steps I followed in doing this project.

  • At first, I was pointed to FPGA Implementation of WARP-V core by Steve, similar to MYTH core but it’s highly parameterized with more stages.
  • Next, to convert TLV code of my core to standard HDL language, I used SandPiper SaaS which is the cloud-based microservice edition of SandPiper for open source development which is developed by Redwood EDA. TL-Verilog can be extended to SystemVerilog or Verilog.
  • I have used Zedboard as my FPGA board. So, then I connected the I/Os of the module to Zedboard.
  • Then comes the 3 major steps to generate a bitstream for Zedboard
  • Synthesis: Generates gate-level netlist
  • Implementation: Optimization, Placement, and Routing
  • Generate Bitstream

For these steps, I have written a TCL script over here.
To directly run the complete flow from TLV to FPGA, I have written a shell script over here.

While doing this project, I stumbled over several obstacles, and with some help from Steve Hoover and Shivam Potdar, another mentor with TL-Verilog experience, found that there were easy resolutions to all of them and some new capabilities that simplify things in the RTL domain. As I am more familiar and comfortable working with Verilog, I converted TLV to Verilog. But while compiling the generated Verilog code, I ran into syntax errors. These were because the workshop was designed for SystemVerilog. So, I just had to rewrite the parts that used SystemVerilog expression syntax and types using Verilog syntax and types. Also, I have discussed a few minor syntax issues with Steve and he has incorporated them in the new release of SandPiper.

How to structure code to be compatible inside and outside of Makerchip?

Makerchip is currently limited to single file editing, so use TLV for main module and connect the I/Os of this main module to FPGA and provide a test bench module for Makerchip. I have also created a template file to start with FPGA flow where I have connected 8-bit output of test module to 8 LED pins on Zedboard in a constraint file. While working on this project, FPGA flow using TL-Verilog got better because of Makerchip-app, a virtual desktop application. More details on how to use it can be found here. Furthermore, I have also developed a basic example of a counter using TL-Verilog and implemented it on Zedboard which can be found here.

Counter example using Makerchip-app interface

I would like to talk about 2 different approaches to use TL-Verilog

  • If you are already developing FPGA logic using Verilog, it will be easy to enable TL-Verilog in your flow.
  • If you are starting it from scratch directly use TL-Verilog and Makerchip from the start as mentioned over here

Current Limitations

  • There is not yet much information about TL-Verilog in the developer community like Stack Overflow, Reddit, Stack Exchange, etc.
  • Makerchip is limited to single file editing. But, soon it will have multi-file support as well.
  • Makerchip and SandPiper SaaS are available only for code with a permissive open-source license.

This will be a kickstart for you to start working on your own FPGA project using TL-Verilog. Hopefully, you will also feel that TL-Verilog is simple, powerful, and flexible which makes it just awesome!! This will indeed impact the current FPGA classrooms using standard HDL language to switch to using TL-Verilog for FPGA classrooms in Makerchip.

More details on my project of using TL-Verilog for FPGAs can be found here:

Also, a demonstration of this RISC-V on FPGA can be found here:

Computer hardware enthusiast | Research Student at IIIT Bangalore